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Wafer-level Reliability Evaluation

Reliability evaluation using TEG is highly effective for evaluation of semiconductor circuits as complex as products because it is difficult to narrow down process reliability problems in particular. It is crucial to detect reliability problems likely to come up in the product stage as early as possible and to inform design and process engineers. OKI Engineering's wafer-level reliability evaluation service is so designed as to establish a highly reliable process and to secure product reliability on long term basis.

Wafer-level Reliability Evaluation

The most effective means of reliability evaluation on wafer-level. We offer measuring service for various parameters of TEG wafer gate oxide films, such as TZDB, TDDB, hot carrier, etc.

ADVANTAGES:

  • Applicable to minute peak current (1E - 13A) measuring
  • One-stop solution from measurement to data processing
  • Measurement of any wafer size starting from a single unit

Characteristics

The key feature is evaluation of TEG data for each failure mechanism assumed beforehand using a proprietary measurement program.

  • Effective acquisition of large data amounts using a proprietary program
  • Reduction of evaluation time by execution of accelerated tests
  • Enables reliability evaluation of process parameters on wafer level

Applications

  • Fast launch of a highly reliable process from the development stage supported by TEG:
    • Process reliability evaluation preceding product and TEG reliability tests
    • Reliability stability and variability evaluation during development process
    • Class curve and confirmation evaluation at process selection
  • Reliability monitor TEG in production stage to production process:
    • Preventive detection of reliability problems
    • Reliability stability monitoring during the production process
    • Judgements of advisability for process modification

Evaluation Example of Damage TEG Wafer Gate Oxide Film

The illustration below introduces an evaluation example of gate oxide of a damaged TEG wafer during pre-process plasma device development. The evaluation case example introduces TZDB (Time Zero Dielectric Breakdown) and TDDB (Time Dependent Dielectric Breakdown) each for unprocessed, plasma process A and plasma process B (from the left column to the right). The TZDB evaluation clearly shows substantial damage of the gate oxide film in plasma process B, while the TDDB evaluation measures the variance between the unprocessed product (margin not measured by TZDB) and plasma process A.

 

TZDB Condition:
0 to 10V at gate oxide film (4μm2), measured 1μA applied voltage leak current in 0.2V intervals.
TDDB Condition:
10nA constant current stress applied to gate oxide film (4μm2), time to damage measured.
Wafer kindly provided by Philtech Inc.

MOSFET Hot Carrier Evaluation Example

Alongside shrinking processes the electric field strength in the vicinity of a FET drain negatively affects the FET's characteristics since the highly energized carrier (hot carrier and electron hole) transfuses into the gate oxide.

Hereafter, we demonstrate a case example of 'hot carrier' evaluation. Specifically, a voltage stress of Vg < Vd is applied and changes in Vth (threshold voltage), etc. are measured.

Figure 1
The basic structure of a MOSFET (hot career injected into the gate oxide).
Figure 2
Id-Vd and Id-Vg/Gm characteristics which are basic to FETs.
Figure 3
Id-Vd and Vth characteristics after release of stress exposure, calculated from Vg at maximum value of Gm, hence observing changes of Id and Vth.


Figure 1


Figure 2


Figure 3

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