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Latch-up Tests

Latch-up Tests

Within the internal structure of CMOS devices, parasitic bi-polar transistor circuits can form structures equivalent to thyristor structures which, when triggered and turned on by extrinsic surge, etc., cause continuous large current flow. These tests are for evaluation of resistance (immunity) to the phenomena where continuously flowing large currents cause latch-up.

  • We provide latch-up tests in compliance with national and international official test standards (table 1).
  • We also provide answers to questions regarding standards and propose a test plan based on the number of samples.
  • We accept production of dedicated test boards (Figure 2) for the test equipment (Figure 1).
  • As of July 2009, we provide 70 types of multi-purpose latch-up test boards.
  • Sockets are required for board production. If not in hands, we can take care of the logistics from order to arrangement.

Table 1: Latch-up Test Standards

Test Method Compliant Standard Essential Test Conditions
Japan U.S.A. Europe
General Automotive
Pulse current injection
I-Test
JEITA ED4701 300-2 JESD 78B AEC-Q100-004 IEC 60749-29
  • Pulse width: 10µs ~ 1s.
  • Number of pulses: 1x, single polarity.
  • Ambient test temperature: room temperature or maximum guaranteed operating temperature.
Power Supply Overvoltage Test
Capacitor discharge
C-Charge Test
EIAJ commission internal data
AB-6201 (1987)
- - -
  • Discharge capacity = 200pF, discharge resistance = 0Ω.
  • Number of pulses: device-dependent.
  • Ambient test temperature: device-dependent.

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