ESD Protection Design
The high-tech device structure adopted to support the rapid development of semiconductor devices for higher speed and lower power consumption has a structure that is very vulnerable to static electricity, causing damage or malfunction resulting from ESD （Electro - static discharge）. As miniaturization of element progresses, it is more difficult to withstand ESD than ever, and the interest in the development of an optimum ESD protective circuit and element is increasing. OKI Engineering Co., Ltd. Offers unique and new consultation service concerning protection against ESD.
ESD/Latch-up test service
Oki Engineering Co., Ltd. conducts tests based on various public standards （JEITA, JEDEC, IEC, etc.） concerning ESD damage and malfunction resistance of electronic devices and electronic equipment as part of commissioned test of an IECQ independent testing laboratory. We also offer various CDM tests services using the FICDM test equipment.
FI-CDM test equipment
ESD:Electro-Static-Discharge
Test method for charged device model
| Test method for charged device model | ||
|---|---|---|
| HBM/MM test |
JEITA ED4701 | |
| JEDEC JESD22-A114/A115 |
||
| ESDA STM5.1/5.2 | ||
| AECQ100-002/3 | ||
| IEC61340-3-1/2 IEC60749-26/27 |
||
| D-CDM test （Charged device method） |
JEITA ED4701ESDA | |
| STM5. 3AECQ100-011 |
||
| IEC60749-28 | ||
| FI-CDM test （Field-induced charged device method） |
JEDEC JESD22-C101C |
|
| ESDA STM5.3 | ||
| AECQ100-011 IEC60749-28 |
||
| Latch-up test （Current injection method/Power overvoltage method） |
JEDEC/EIA JESD78 | |
| JETA ED4701 AEC-9100-004 |
||
| Latch-up test （Capacitor charging method） |
EIAJ -ED4701 Technical data AB6201 |
|
- HBM:human body model
- Damage to device due to discharge of static electricity accumulated on human body
- MM:machine model
- Damage to device due to discharge of static electricity accumulated on metal, etc.
- CDM:charged device model
- Damage to device due to electro - static discharge （ESD） that occurs when the device is charged directly or indirectly, and when the terminal contacts with a conductor with different electric potential.
Public standard for system level: ESD-Immunity test
| Public standard for system level: ESD-Immunity test | ||
|---|---|---|
| IEC standards | IEC61000-4-2 | |
| JASO standards | JASO D-010 （ISO） | |
Consultation about in-process ESD （Electro - static discharge）
When ESD （Electro - static discharge） breakdown is presumed based on the analysis of rejected parts in the electronic component assembly process, we retest and reexamine the in-process ESD to propose a solution for preventing from ESD breakdown.
Analysis of ESD （Electro - static discharge） breakdown mechanism using failure analysis
Consultation about static electricity control and measures to cope with static electricity in the assembly process
OKI Engineering Co., Ltd. supports materialization of static electricity control and measures to cope with static electricity based on the public standard （IEC61340-5-1/5-2） for electronic component assembly, as well as assessment of the performance of antistatic materials and fixtures. We assess the various ESD resistance characteristic values of our customers’ devices and propose measures to prevent from and control in-process electrostatic accidents.
- Materialization of measures to cope with in-process static electricity to support quality certification and inspection
- Support for creation of static electricity control rules
Consultation about ESD protection design
OKI Engineering Co., Ltd. extracts ESD parameters of our customers’ processes necessary for ESD protection design for semiconductor devices, provides an optimum ESD protection circuit that matches the respective terminal characteristics and supports ESD protection design of products. For that purpose, we use our original ESD protection design technique based on the TDR-TLP measuring method. In addition, we support our customers’ request for latch-up protection design and IO design guidelines creation.
- Consultation about TEG design for parameter extraction
- Consultation about optimum ESD protection design technique
- Consultation about ESD protection product design
- Consultation about Latch-up durability design
- Capitalization of ESD durability design（Spice-Sim/Mix-mode-Sim Modeling）
